WM8994ECSSLASHR datasheet(75/363 Pages) CIRRUS

75 / 363 page

WM8994

Rev 4.6

The “Knee1” point in Figure 24 is determined by register fields [DRC]_KNEE_IP and

[DRC]_KNEE_OP.

Parameter Y0, the output level for a 0dB input, is not specified directly, but can be calculated from the

other parameters, using the equation:

Y0 = [DRC]_KNEE_OP

– ([DRC]_KNEE_IP * [DRC]_HI_COMP)

GAIN LIMITS

The minimum and maximum gain applied by the DRC is set by register fields [DRC]_MINGAIN,

[DRC]_MAXGAIN and [DRC]_NG_MINGAIN. These limits can be used to alter the DRC response

from that illustrated in Figure 24. If the range between maximum and minimum gain is reduced, then

the extent of the dynamic range control is reduced.

The minimum gain in the Compression regions of the DRC response is set by [DRC]_MINGAIN. The

mimimum gain in the Noise Gate region is set by [DRC]_NG_MINGAIN. The minimum gain limit

prevents excessive attenuation of the signal path.

The maximum gain limit set by [DRC]_MAXGAIN prevents quiet signals (or silence) from being

excessively amplified.

DYNAMIC CHARACTERISTICS

The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note

that the DRC responds to the average (RMS) signal amplitude over a period of time.

The [DRC]_ATK determines how quickly the DRC gain decreases when the signal amplitude is high.

The [DRC]_DCY determines how quickly the DRC gain increases when the signal amplitude is low.

These register fields are described in Table 24, Table 25 and Table 26. Note that the register defaults

are suitable for general purpose microphone use.

ANTI-CLIP CONTROL

The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very

quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal

clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip feature

is enabled using the [DRC]_ANTICLIP bit.

Note that the feed-forward processing increases the latency in the input signal path.

Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent

signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be

prevented by reducing the analogue signal gain or by adjusting the source signal.

Note that the Anti-Clip feature should not be enabled at the same time as the Quick Release feature

(described below) on the same DRC.

WM8994ECS/R 데이터시트(PDF) 75 Page - Cirrus Logic