SDA

SCL

S

P

START condition

STO

P condition

S

1

2

3...6

7

8

9

Start

Condition

Acknowledge Signal

from Receiver

Transmitter Stays off the

Bus During the

Acknowledge Clock

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

26

LP55281

SNVS458D – JUNE 2007 – REVISED OCTOBER 2016

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Copyright © 2007–2016, Texas Instruments Incorporated

Programming (continued)

7.5.2.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the SCL.

Consequently, throughout the clock's high period, the data should remain stable. Any changes on the SDA line

during the high states of the SCL and in the middle of the transaction, aborts the current transaction. New data

should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

Figure 20. Data Validity

Each data transaction is composed of a start condition, a number of byte transfers (set by the software) and a

stop condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an acknowledge signal must follow. The following

sections provide further details of this process.

Figure 21. Acknowledge Signal

The Master device on the bus always generates the start and stop conditions (control codes). After a start

condition is generated, the bus is considered busy and it retains this status until a certain time after a stop

condition is generated. A high-to-low transition of the data line (SDA), while the clock (SCL) is high, indicates a

Start Condition. A low-to-high transition of the SDA line, while the SCL is high, indicates a stop condition.

Figure 22. Start And Stop Conditions