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LP55281TL/NOPB 데이터시트(PDF) 9 Page - Texas Instruments |
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LP55281TL/NOPB 데이터시트(HTML) 9 Page - Texas Instruments |
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9 / 42 page ![]() SCK Data BIT 1 LSB IN LSB OUT BIT 1 MSB OUT BIT 7 BIT 8 BIT 9 BIT 14 MSB IN R/W Address 2 1 4 5 7 6 3 11 9 10 8 SS SO SI 12 9 LP55281 www.ti.com SNVS458D – JUNE 2007 – REVISED OCTOBER 2016 Product Folder Links: LP55281 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated (1) Data ensured by design. 6.6 SPI Timing Requirements VDD = VDDIO = 2.8 V (1) MIN MAX UNIT 1 Cycle time 70 ns 2 Enable lead time 35 ns 3 Enable lag time 35 ns 4 Clock low time 35 ns 5 Clock high time 35 ns 6 Data setup time 20 ns 7 Data hold time 0 ns 8 Data access time 20 ns 9 Disable time 10 ns 10 Data valid 20 ns 11 Data hold time 0 ns Figure 1. SPI Timing Diagram |
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