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LP55281

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SNVS458D – JUNE 2007 – REVISED OCTOBER 2016

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10 Layout

10.1 Layout Guidelines

The inductive boost converter of the LP55281 regulates a switched voltage at the SW pin, and a step current (up

to ICL) through the Schottky diode and output capacitor each switching cycle. The switching voltage can create

interference into nearby nodes due to electric field coupling (I = CdV/dt). The large step current through the diode

and the output capacitor can cause a large voltage spike at the SW pin and the OUT pin due to parasitic

inductance in the step current conducting path (V = Ldi/dt). Board layout guidelines are geared towards

minimizing this electric field coupling and conducted noise.

The following list details the main (layout sensitive) areas of the LP55281 device's inductive boost converter in

order of decreasing importance:

•

Output Capacitor

–

Schottky cathode to COUT+

–

COUT– to GND

•

Schottky Diode

–

SW pin to Schottky anode

–

Schottky Cathode to COUT+

•

Inductor

–

SW Node PCB capacitance to other traces

•

Input Capacitor

–

CIN+ to IN pin

10.1.1 Boost Output Capacitor Placement

Because the output capacitor is in the path of the inductor current discharge path it detects a high-current step

from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Any parasitic inductance (LP_)

along this series path from the cathode of the diode through COUT and back into the GND pin of the LP55281

device GND pin contributes to voltage spikes (VSPIKE = LP_ × di/dt) at SW and FB. These spikes can

potentially over-voltage the SW pin, or feed through to GND. To avoid this, COUT+ must be connected as close

as possible to the cathode of the Schottky diode, and COUT

− must be connected as close the the GND pin of

the device as possible. The best placement for COUT is on the same layer as the LP55281 in order to avoid any

vias that can add excessive series inductance.

10.1.2 Schottky Diode Placement

In the boost circuit of the LP55281 device the Schottky diode is in the path of the inductor current discharge. As

a result the Schottky diode sees a high-current step from 0 to IPEAK each time the switch turns off and the diode

turns on. Any parasitic inductance (LP) in series with the diode causes a voltage spike (VSPIKE = LP × di/dt) at

SW and OUT. This can potentially over-voltage the SW pin, or feed through to VOUT and through the output

capacitor and into GND. Connecting the anode of the diode as close as possible to the SW pin and the cathode

of the diode as close as possible to COUT and reduces the parasitic inductance and minimize these voltage

spikes.

10.1.3 Inductor Placement

The node where the inductor connects to the LP55281 device's SW pin has 2 concerns. First, the switched

voltage (0 to VOUT + VF_SCHOTTKY) appears on this node every switching cycle. This switched voltage can be

capacitively coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces

connecting the input supply to the inductor and connecting the inductor to the SW bump. Any resistance in this

path can cause voltage drops that can negatively affect efficiency and reduce the input operating voltage range.

To reduce the capacitive coupling of the signal on SW into nearby traces, the SW bump-to-inductor connection

must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, high

impedance nodes that are more susceptible to electric field coupling need to be routed away from SW and not

directly adjacent or beneath. This is especially true for sensitive analog signals (ASE1, ASE2, FB, IRT, IRGB,

VREF). A GND plane placed directly below SW dramatically reduces the capacitance from SW into nearby

traces. Lastly, limit the trace resistance of the VIN to inductor connection and from the inductor to SW

connection, by use of short, wide traces.