VS6724 datasheet(97/118 Pages) STMICROELECTRONICS

97 / 118 page

VS6724

Programming model and register description

97/118

0x23b0

bPClkSetup

Default value

0x05

Type

CODED

flag bits

[0] PClkSetup_prog_lo

1-> Rising Edge of PCLK

0-> Falling Edge of PCLK

[1] PClkSetup_prog_hi

1-> Polarity of PLCK normally high

0-> Polarity of PLCK normally low

[2] PClkSetup_sync_en

1-> Enable PCLK during Embedded sync codes

0-> Disable PCLK during Embedded sync codes

[3] PClkSetup_hsync_en_n

1-> enable the PCLK outside the HSYNC active period

0-> disable the PCLK outside the HSYNC active period

[4] PClkSetup_hsync_en_n_track_internal

1-> use the internal tracked hsync for the qualification of the bit[3]

0-> use the manually set hsync for the qualification of the bit[3]

[5] PClkSetup_vsync_n

1-> enable pclk outside VSYNC active period

0-> disable pclk outside VSYNC active period

[6] PClkSetup_vsync_n_track_internal

1-> use the internal tracked vsync for the qualification of the bit[5]

0-> use the manually set vsync for the qualification of the bit[5]

[7] PClkSetup_freer

1-> Set the PCLK to free run

0 ->Set the PCLK to be controlled

0x23b2

fPclkEn

Default value

<1> TRUE

Type

Flag_e

Possible values

<0> FALSE

<1> TRUE

Changes only consumed during a change to RUN mode

Table 47.

Output control (continued)

Index

OutputControl(1)

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