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VS6724 데이터시트(PDF) 40 Page - STMicroelectronics |
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VS6724 데이터시트(HTML) 40 Page - STMicroelectronics |
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40 / 118 page ![]() Functional description VS6724 40/118 2.11.3 Derating When the scaler is operating the clock manager employs derating to reduce the peak output rate of the device by spreading the data over the full frame period. The derating employed can be found by dividing the input size to the scaler by the output size of the scaler and rounding up to the nearest even number. Example: VGA output scaled from the full UXGA array = 1600x1200 / 640x480 = 6.25 rounded up to the nearest even number = 8, therefore the VGA output is 8 times slower than that for the full UXGA output. |
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