VS6724 datasheet(39/118 Pages) STMICROELECTRONICS

39 / 118 page

VS6724

Functional description

39/118

2.11

Timing control

2.11.1

Input clock

The VS6724 requires provision of an external reference clock. The external clock should be

a DC coupled square wave and may have been RC filtered. The clock input is fail-safe in

power down mode.

The VS6724 contains an internal PLL allowing it to produce accurate frame rates from a

wide range of input clock frequencies. The allowable input range is from 6.5 MHz to 27 MHz.

The external clock frequency must be programmed in the registers found in

Table 19: Video

timing parameter host inputs.

2.11.2

PLL operation

The VS6724 contains a firmware based programmable timing generator which automatically

configures the internal video timing, PLL multipliers, clock dividers to achieve a target

operation. The timing generator is controlled and constrained by the required PLL

frequency, framerate and scaling factor, this in turn effects the output PCLK frequency.

Timing control

The bSysClkMode register selects the mode in which the system clock manager works,

●

<0> SYSCLK_MODE_NORMAL

●

<1> SYSCLK_MODE_USER

In normal mode the VS6724 can achieve UXGA at 30 fps and is based on an internal PLL

frequency of 260 MHz, the clock management system ensures a maximum output

frequency of 80 Mhz (YCbCr).

In user mode the VS6724 can be configured to allow the VS6724 to meet the input

frequency constraints of a host application. The fpUserPLLCLK register sets the maximum

frequency generated by the system clock manager and therefore limits the output frequency

and is based on the following equation:

fpUserPLLClk = 2 * PCLKmax

The PCLKmax may be a limitation on the host and using the following approximate

calculation can help work out the framerate achievable with this output PCLK rate;

Framerate = PCLKmax / (Image size * data format * 1.10)

●

Image size = 1600 x 1200 for UXGA sensor mode

●

Image size = 800 x 600 for SVGA sensor mode

●

Data format = 2 for YCbCr 4:2:2, RGB and Bayer10 (as these are 2 Bytes per pixel)

●

Data format = 1 for YCbCr 4:2:0 and Bayer 8 (as these are 1 Byte per pixel)

●

(1.10) is a 10% increase to take into account interline and interframe.

VS6724 데이터시트(PDF) 39 Page - STMicroelectronics

VS6724 데이터시트(HTML) 39 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL