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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VS6724 데이터시트(PDF) 102 Page - STMicroelectronics |
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VS6724 데이터시트(HTML) 102 Page - STMicroelectronics |
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102 / 118 page  Programming model and register description VS6724 102/118 0x2514 bOIFCLKRatio Default value 0x1 Purpose Determines the maximum PCLK output rate for the JPEG data, in relation to the YUV pixel clock frequency Type BYTE Possible values 0 ->PCLK is same frequency YUV pixel clock, for non JPEG //for JPEG 1-> PCLK is 2 times slower 2-> PCLK is 4 times slower 3-> PCLK is 6 times slower 4-> PCLK is 8 times slower 5-> PCLK is 10 times slower 6-> PCLK is 12 times slower 7-> PCLK is 14 times slower 8-> PCLK is 16 times slower 9-> PCLK is 18 times slower 10-> PCLK is 20times slower 0x251b 0x251c uwThres Default value 0x0200 Purpose Sets the number of bytes of JPEG data are present in each Packet (line), must equal uwLinelength Type WORD Possible values The number of bytes in a line is 2 x the value programmed into this register, the maximum number of bytes in a line is 2KB. 1. Can be controlled in all stable states Table 50. JPEG image characteristics (continued) Index JPEGImageCharacteristics(1) |
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