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TLC320AD50C/I 데이터시트(PDF) 48 Page - Texas Instruments |
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TLC320AD50C/I 데이터시트(HTML) 48 Page - Texas Instruments |
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48 / 54 page ![]() 7–1 7 Application Information DVDD TMS320C2x/3x/5x/2xx/54x CLKOUT DX DR FSX FSR CLKX CLKR TLC320AD50C MCLK DIN DOUT FS SCLK FSD TLC320AD50C MCLK DIN DOUT FS SCLK FSD Master Mode Slave Mode XF FC FC M/S M/S Figure 7–1. Master Device and Slave Device Connections (to DSP Interface) When multiple AD50’s or AD52’s are attached to a single DSP serial interface in a master/slave configuration, the control registers should be programmed in the following order during device initialization: Control register 1 Control register 2 Control register 4 Control register 3 All AD50 or AD52 devices will be configured the same with a single global initialization being written to registers 1, 2, and 4. Once register 3 is programmed (setting the number of SCLKS between FS and FSD), each device will begin communicating in its designated time slot. |
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