IP1000A LF
Preliminary Data Sheet
36/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
after reaching 0xFFFF. See IEEE 802.3 Clause
30.3.1.1.15.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
FramesLostRxErrors reaches a value of 0xC000.
FramesLostRxErrors is enabled by writing a logic
1 to the StatisticsEnable bit in the MACCtrl
register, and a logic 0 to the FramesLostRxErrors
bit within the StatisticsMask register.
3.2.1.9
FramesRcvdOk
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xB4
Default Value ................ 0x00000000
Access Rule.................. Double Word
Width ............................ 32 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
31..0
FramesRcvdOk
Frames Received OK is the count of the number
of
frames
that
are
successfully
received.
FramesRcvdOk
does
not
include
frames
received with frames too long, FCS, length or
alignment errors, or frames lost due to internal
MAC sublayer error (i.e. overrun). FramesRcvdOk
will
wrap
around
to
zero
after
reaching
0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.5.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
FramesRcvdOk reaches a value of 0xC0000000.
FramesRcvdOk is enabled by writing a logic 1 to
the StatisticsEnable bit in the MACCtrl register,
and a logic 0 to the FramesRcvdOk bit within the
StatisticsMask register.
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