IP1000A LF
Preliminary Data Sheet
50/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.2.6
ConfigStatus
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x06
Default Value ................ 0x0230
Access Rule.................. Word
Width ............................ 16 bits
ConfigStatus is used to record status information for PCI bus events. Read/write bits within ConfigStatus
can only be set to a logic 0, not to a logic 1. Bits are set to a logic 0 by writing a logic 1 to the appropriate bit.
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
2..0
Reserved
Reserved for future use. Write as zero, ignore on read.
N/A
3
IntStatus
Interrupt Status. IntStatus reflects the state of the
interrupt of the IP1000A LF. Only when the
Interrupt Disable bit in the command register is a
logic 0 and IntStatus is a logic 1, will the IP1000A
LF’s INTAN signal be asserted. Setting the
Interrupt Disable bit to a 1 has no effect on the
state of IntStatus.
R
4
CapabilitiesList
Capabilities List. CapabilitiesList is a logic 1 to
indicate a set of extended capabilities registers
exists for the IP1000A LF. The CapPtr register
indicates the first address location of the extended
capabilities register set.
R
5
66MHzCapable
66MHz Capable. When 66MHzCapable is a logic
1 operation of the IP1000A LF PCI bus interface at
66MHz is supported.
R
6
Reserved
Reserved for future use. Write as zero, ignore on read.
N/A
7
FastBackToBack
Fast Back to Back. When FastBackToBack is a
logic 1 the IP1000A LF when operating as a
Target, supports fast back-to-back transactions as
defined by the criteria in the section 3.4.2 of the
PCI specification.
R
8
MasterDataParity
Error
Master
Data
Parity
Error.
When
MasterDataParityError is a logic 1, the IP1000A
LF when operating as a Master, has detected the
PERRN
signal
asserted,
and
the
ParityErrorResponse bit in the ConfigCommand
register as a logic 1.
Note: If the IP1000A LF is initialized to PCI-X
mode, MasterDataPari-tyError is set in either the
initiator or target under the following conditions:
The initiator (requester) of a read transaction that
is completed immediately calculates a data parity
error.
The
initiator
(requester)
of
a
read
transaction that is terminated with Split Response
calculates
a
data
parity
error
in
the
Split
Response. The initiator (requester) of a write that
is
comleted
immediately
observes
PERRN
asserted three clocks after one or more of its data
phases. The initiator (requester) of a write that is
R
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