IP1000A LF
Preliminary Data Sheet
37/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.1.10 FramesWDeferredXmt
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xE4
Default Value ................ 0x00000000
Access Rule.................. Double Word
Width ............................ 32 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
31..0
FramesWDeferred
Xmt
Frames with Deferred Transmit is a count of the
number of frames that must delay their first attempt
of transmission because the medium was busy.
Frames involved in any collisions are not counted
by FramesWDeferredXmt. FramesWDeferredXmt
wrap around to zero after reaching 0xFFFFFFFF.
See IEEE 802.3 Clause 30.3.1.1.9.
An UpdateStats interrupt (UpdateStats bit within the
IntStatus
register)
will
occur
when
FramesWDeferredXmt
reaches
a
value
of
0xC0000000. FramesWDeferredXmt is enabled by
writing a logic 1 to the StatisticsEnable bit in the
MACCtrl
register,
and
a
logic
0
to
the
FramesWDeferredXmt bit within the StatisticsMask
register.
R/W
3.2.1.11 FramesWEXDeferal
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xFE
Default Value ................ 0x0000
Access Rule.................. Word
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
15..0
FramesWEXDe-
feral
Frames with Excessive Deferals counts the
number of frames that deferred for an excessive
period
of
time
(exceeding
the
defer
limit).
FramesWEXDeferal is only incremented once per
LLC frame. FramesWEXDeferal will wrap around
to zero after reaching 0xFFFF. See IEEE 802.3
Clause 30.3.1.1.20.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
FramesWEXDeferal reaches a value of 0xC000.
FramesWEXDeferal is enabled by writing a logic 1
to the StatisticsEnable bit in the MACCtrl register,
and a logic 0 to the FramesWEXDeferal bit within
the StatisticsMask register.
R/W
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