ADC08B200

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SNAS388F – MARCH 2007 – REVISED APRIL 2013

FUNCTIONAL DESCRIPTION

The ADC08B200 integrates an 8-bit, high speed ADC and a configurable capture buffer of up to 1 kilobyte,

allowing the sampling and processing tasks to be independent of each other. This functionality is intended for

those applications that need to sample an input signal at a high rate and then read the collected samples at a

slower rate. The Timing Diagrams illustrate the operation of the ADC08B200.

The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Input voltages

below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word

to consist of all ones.

The ADC08B200 exhibits a power consumption that is proportional to frequency, limiting power consumption to

what is needed at the clock rate that is used. This, its excellent performance over a wide range of clock

frequencies and the incorporation of a capture buffer make ADC08B200 an ideal choice for many 8-bit ADC

applications.

Data is acquired at the rising edge of the sample clock and, in the buffer bypass mode, the digital equivalent of

that data is available at the digital outputs 6 clock cycles plus tOD later. When the Buffer is enabled, the

converted data is written to the buffer with each internal conversion clock cycle and can be read out with the

RCLK signal. The ADC08B200 will convert as long as a CLK signal is present, but when using the buffer no

writing to the buffer will occur when that buffer is full. The output coding is straight binary.

The entire device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the entire

device is in the power down mode, consuming very little power. Holding the clock input low after raising the

Power Down pin will further reduce the power consumption in the power down mode.

When the PDADC pin is high, only the A/D converter itself is in the power down mode. The rest of the chip is left

powered up so that the capture buffer may be read. If both the PD and PDADC pins are high, the PD pin

dominates and the entire device is powered down.

The A/D converter sample clock can be either the clock signal at the CLK input pin or a multiplied version of that

clock. The clock multiplier can be 2, 4 or 8. In any case, the sample clock is also used to write the converter data

into the capture buffer when that buffer is used.

As long as the chip is not in a power down state and there is a clock signal present, the A/D converter is

converting the input signal. However, the data is stored into the capture buffer, when the buffer is used, only

while the Write Enable (WEN) input is high. The data is read from the capture buffer with the RCLK signal, which

can be a free running clock, while the Read Enable (REN) signal is high.

Note that the capture buffer on this chip must be entirely filled to its configured size before reading its contents

can begin. It is not possible to write to and read from the buffer at the same time and the WEN and REN inputs

should not be high at the same time. If they are high at the same time, the REN input is ignored. This is true

even if the REN input is high first and a read operation is progressing normally when the WEN input goes high.

Asserting the WEN input while REN is high will cause the read operation to be aborted, an internal buffer reset to

be issued (resetting the pointers) and a capture operation to begin. Although this device is intended for fast

capture and slower read out applications, it is possible for the RCLK to operate at the same rate or faster than

the sample clock.

Two status flags are provided to manage the capture buffer. As the name suggests, the Full Flag (FF) goes high

when the buffer is full. The next sample clock rise after the assertion of FF will begin writing over the oldest data

because the write pointer will "wrap around". This is called an "over run" condition. Similarly, the Empty Flag (EF)

indicates that the last of the data has been read and the buffer is empty. When EF goes high, the DRDY and

Data outputs stop switching and both DRDY and the Data lines remain low if OEDGE=1. Both remain high if

OEDGE=0.

The user has the option to stop writing to the buffer automatically upon a buffer full condition with the use of the

ASW (Auto Stop Write) input. If the ASW input is low, the buffer will be continually written to, resulting in the

possibility of the write pointer "wrapping around" and the data continually being overwritten as long as there is a

clock and the WEN input is high. If the ASW input is high, the write operation stops upon reaching the "full"

condition.

FF goes low upon device reset and when the "full" condition is removed by starting a transfer operation with the

assertion of REN. The EF output goes low when the "empty" condition is removed by starting a capture operation

with the raising of WEN. The EF output goes high upon device reset because resetting empties the buffer.

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