ADC08B200

SNAS388F – MARCH 2007 – REVISED APRIL 2013

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Figure 48. Isolating the ADC Clock from Digital Circuitry

It is good practice to keep the ADC clock line as short as possible and to keep it well away from other signals,

which can introduce jitter into the clock signal. The clock signal can also introduce noise into a nearby signal

path.

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should

not go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits on

even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits

(e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A 47

Ω resistor in

series with the offending digital input, close to the driving source, will usually eliminate the problem.

Care should be taken not to overdrive the inputs of the ADC08B200. Such practice may lead to conversion

inaccuracies and even to device damage.

Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must

charge for each conversion, the more instantaneous digital current is required from VDR and DR GND. These

large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the

digital data outputs may be necessary if the data bus capacitance exceeds 10 pF. Dynamic performance can

also be improved by adding 12

Ω to 27Ω series resistors at each digital output, reducing the energy coupled back

into the converter input pins.

Using an inadequate amplifier to drive the analog input. As explained in THE ANALOG INPUT, there are

voltage spikes at the ADC analog input. These voltage spikes can cause instability in a feedback type amplifier

used to drive the analog input. These spikes need not be filtered out, but should settle quickly. The amplifier

should be fast enough to handle the frequencies presented to it, but not so fast that it would readily oscillate. A

single-pole RC filter, as explained in THE ANALOG INPUT will help ensure amplifier stability and accurate data

capture.

Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the

ladder. As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source

sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with

devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of

dynamic performance.

Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR performance. The use of simple gates with RC timing is generally

inadequate as a clock source.

Busing the data outputs. SNR performance of all ADCs, especially high speed ADCs, is sensitive to the

amount of capacitance at the data outputs because the currents required of the ADC data outputs to charge and

discharge these capacitances cause voltage spikes (noise) on the die. Minimizing the output capacitance will

help maintain noise performance of the converter. Busing the outputs adds undesired capacitive loading to the

ADC. Similarly, it is important to keep trace capacitance to a minimum by using short traces at the ADC outputs.

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