ADC08B200

SNAS388F – MARCH 2007 – REVISED APRIL 2013

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The WEN (Write Enable) input is used to enable writing to the buffer, while the REN (Read Enable) input is used

to enable reading from the buffer. If both of these are high, the WEN input dominates and the REN input is

ineffective until WEN goes low. If the WEN pin remains high after the buffer is full, the previous contents are

over-written. The ASW (Auto-Stop Write) pin may be used to automatically stop writing to the buffer when it is full

to the configured number of bytes. See THE WEN PIN, THE REN PIN, and THE ASW PIN for information on

these inputs.

The BSIZE inputs are used to configure the Data Buffer size (described in Table 2). The user has a choice of

using the buffer or bypassing it.

When the buffer is used and its contents have been read, the DRDY and the Data Outputs maintain the opposite

sense of the OEDGE input. When the buffer is bypassed, it is not used and the data is presented at the ADC

data output pins at the same rate as the sample clock. Table 2 indicates the choices available and the BSIZE pin

settings to achieve each.

When the buffer is bypassed (both BSIZE pins low), the ADC output is sent directly to the output port at the

sample clock rate without going through the buffer. In this mode all buffer control inputs (WEN, REN, ASW and

RCLK) are ignored and the EF and FF outputs are held low. The DRDY output may be used to capture the data

at the output port.

Table 2. BSIZE Pin Function

BSIZE1

BSIZE0

Buffer Size

0

0

Buffer is bypassed

0

1

256 bytes

1

0

512 bytes

1

1

1024 bytes

Reading the Buffer

There are two options for reading the contents of the ADC08B200 buffer. Since the DRDY output is source-

synchronous with the data output, it may be used to read the buffer data into the receiving device. This buffer

read method works well at any read rate for which the device is capable and is the preferred method of reading

the buffer at read rates greater than about 70 to 80 MHz. When using this method it is important that the DRDY

line electrical length and load are matched with those of the data lines in order to minimize DRDY to data output

skew.

The other read option is to ignore the DRDY signal and use the RCLK signal to read the ADC08B200 buffer. This

method may be easier to implement than is the use of DRDY when using a DSP or processor to read the buffer.

However, because RCLK is not source-synchronous with the data lines, this method is not recommenced for

buffer read (RCLK) rates above about 60 to 70 MHz. Specifications for tOHF + tF / 2and tOHR + tR / 2 provide the

necessary timing information of output data relative to RCLK. Keep in mind that the device timing specifications

apply at the device pins. Additional system delays must be taken into account to determine the RCLK to Data

timing relationship at the receiving device.

Regardless of which method is used, RCLK is needed to clock the captured data from the buffer. The buffer can

not be read without RCLK. Likewise reading the test pattern also requires the use of RCLK.

RCLK may be stopped when not reading the buffer and may be stopped in either the high state or the low state.

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