4.7k

0.1 PF

309:

470:

VIN

1/2

LM8272

-

+

1

8

4

3

2

10 PF

+

+3.3V

0.01 PF

1 PF

1/2

LM8272

+

-

6

5

1.62k

0.01 PF

7

604:

LM4040-2.5

0.1 PF

0.1 PF

1 PF

4.7k

1 PF

8 11

GND

ADC08B200

D7

D6

D5

D0

D1

D2

D3

D4

6

3

5

30

DR GND

10

VRT

VIN

2

46

CLK

9

0.1 PF

10 PF

+

1 4

32

0.1 PF

10 PF

VDR

VA

Choke

0.1 PF

10 PF

+

12

7

VIN GND

38

MUL0

39

MUL1

BSIZE0

BSIZE1

24

23

DRDY

31

OE

40

OEDGE

14

EF

15

FF

16

REN

20

WEN

17

21 42 45 47

43

44 48

+

10 PF

0.1 PF

VP

RCLK

19

ASW

25

18

WENsync

37

RESET

22

VD

PD

13

26

27

28

36

35

34

33

29

PDADC

41

VRM

VRB

+3.3V

ADC08B200

www.ti.com

SNAS388F – MARCH 2007 – REVISED APRIL 2013

The LM8272 was chosen because of its rail-to-rail input and output capability, its high output current capability

and its ability to drive large capacitive loads.

The divider resistors at the inputs to the amplifiers could be changed to suit the application reference voltage

needs, or the divider can be replaced with potentiometers or DACs for precise settings. The bottom of the ladder

(VRB) may be returned to ground if the minimum input signal excursion is 0V.

VRT should always be at least 0.5V more positive than VRB. While VRT may be as high as the VA supply voltage

and VRB may be as low as ground, the difference between these two voltages (VRT − VRB should not exceed 2.3V

to prevent a slight waveform distortion.

The VRM pin is the center of the reference ladder and should be bypassed to a quiet point in the ground plane

with a 0.1 µF capacitor. DO NOT leave this pin open and DO NOT load this pin with more than 10µA.

Figure 45. Driving the Reference to Force Desired Values Requires Driving with a Low Impedance

Source

THE ANALOG INPUT

The analog input of the ADC08B200 is a switch followed by an integrator. The input capacitance changes with

the clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. The sampling nature

of the analog input causes current spikes at the input that result in voltage spikes there. These spikes are normal

and need not be eliminated. However, any amplifier used to drive the analog input must be able to settle within

the clock high time. Using a single pole RC filter between the amplifier and the ADC input will minimize the

effects of these transients on the driving amplifier. The cutoff frequency of this filter should be approximately the

same as the ADC sample rate for Nyquist applications. Choose a capacitor value of 33 pF to 51 pF and a

resistor value according to the formula

Copyright © 2007–2013, Texas Instruments Incorporated

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