DIX4192IPFB datasheet(31/71 Pages) TI2

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DIX4192

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SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

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Figure 28. Register 06: Port B Control Register 2

7 (MSB)

0 (LSB)

BCLK1

BCLK0

BDIV1

BDIV0

Table 9. Register 06: Port B Control Register 2 Field Descriptions

BDIV[1:0]

Port B Master Mode Clock Divider

These bits are used to set the master clock divider for generating the LRCKB clock for Port B when configured for Master mode operation.

BCKB is always set to 64 times the LRCKB clock rate in Master mode.

BDIV1

BDIV0

Master Mode Clock Divider

Divide-by-128 (default)

Divide-by-256

Divide-by-384

Divide-by-512

BCLK[1:0]

Port B Master Clock Source

These bits are used to set the master clock source for Port B when configured for Master mode operation.

BCLK1

BCLK0

Master Clock Source

MCLK (default)

RXCKI

RXCKO

Reserved

Figure 29. Register 07: Transmitter Control Register 1

7 (MSB)

0 (LSB)

TXCLK

TXDIV1

TXDIV0

TXIS1

TXIS0

BLSM

VALID

BSSL

Table 10. Register 07: Transmitter Control Register 1 Field Descriptions

BSSL

Block Start or Asynchronous Data Slip Interrupt Trigger Selection

This bit is used to select the trigger source for the Transmitter TSLIP status and interrupt bit.

BSSL

TSLIP Interrupt Trigger Source

Data slip condition (default)

Block start condition

VALID

Validity (V) Data Bit

This bit may be used to set the validity (or V) data bit in the AES3-encoded output. Refer to the VALSEL bit in control register 0x09 for V-

bit source selection.

VALID

Transmitted Validity (V) Bit Data

Indicates that the transmitted audio data is suitable for conversion to an analog signal or for further digital

processing. (default)

Indicates that the transmitted audio data is not suitable for conversion to an analog signal or for further

digital processing.

BLSM

Transmitter Block Start Input and Output Mode

This bit is used to select the input and output mode for the DIT block start pin, BLS (pin 35).

BLSM

BLS Pin Mode

Input (default)

Output

TXIS[1:0]

Transmitter Input Data Source

These bits are used to select the audio data source for the DIT function block.

TXIS1

TXIS0

Output Word Length

Port A (default)

Port B

DIR

Reserved

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