ADS5294IPFPR datasheet(30/82 Pages) TI2

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ADS5294

SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018

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9.3 Feature Description

9.3.1 Analog Input

The analog inputs consist of a switched-capacitor-based differential sample and hold architecture. This

differential topology results in good AC performance even for high input frequencies at high sampling rates. The

INP and INM pins are internally biased around a common-mode voltage of Vcm (0.95 V). For a full-scale

differential input, each input pin (INP and INM) must swing symmetrically between Vcm + 0.5 V and Vcm – 0.5 V,

resulting in a 2 VPP differential input swing. Figure 44 shows the equivalent circuit of the input sampling circuit.

(1)

SZ MOSFETs' open ends connect to common mode potential, while they don't impact the inputs' loading. Users may

treat the open ends as high impedance nodes.

Figure 44. Analog Input Circuit Model

9.3.2 Input Clock

Figure 45 shows the clock equivalent circuit of the ADS5294. The ADS5294 is configured by default to operate

with a single-ended input clock. CLKP is driven by a CMOS clock and CLKM is tied to GND. The device

automatically detects a single-ended or differential clock. If CLKM is grounded, the device treats clock as a

single-ended clock. Operating with a low-jitter differential clock usually gives better SNR performance, especially

at input frequencies greater than 30 MHz.

ADS5294IPFPR 데이터시트(PDF) 30 Page - Texas Instruments