L9396 datasheet(88/109 Pages) STMICROELECTRONICS

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System functional safety implementations

L9396

88/109

DS12539 Rev 10

reconfigured as scan chains in order to be tested by an internal bist controller. Once µC sets

LOGIC BIST RUN =1 it can perform a polling on BIST_CTRL register (bit 1:0) in order to

read the status of Logic Bist Test.

"01" means BIST RUNNING

"10" BIST PASSED

"11" BIST FAILED

"00" BIST STOPPED

If BIST STATUS is "10" (or "11") the Logic Bist test is finished and passed (or failed).

Microcontroller can write LOGIC BIST RUN = 0 to exit from BIST mode at Logic Bist end

(PASSED or FAILED) but also during the test (BIST RUNNING).

Once LOGIC BIST RUN is set from 1 to 0 the logic under test and SPI registers are reset to

the default condition.

The IC does not take actions if the Logic Bist Test fails. The decision to enable/disable the

drivers and WSS is however given to the µC.

7.8.2

Analog Bist

Analog BIST is performed periodically during normal operation on the overvoltage and

undervoltage monitors of VDD, VINTA, VBST, VPREREG, VCORE, VCOREFDBK, VCC,

VCC5 and Tracking regulators and open of GNDD. In case of ABIST fail, the failing

comparator reports overvoltage or undervoltage or POR is asserted in case of GNDD open.

7.8.3

OTP check

In each power up cycle (POR transition from low to high) the content of internal OTP is

checked. Parity bits have been implemented to monitor the change of state of the trimming

bits. In case check is not completed or not passed a dedicated fault bit is set (OTP_STABLE

bit of ADV_CONFIG register).

Table 59. Logic Bist

Symbol

Parameter

Conditions/Comments

Min.

Typ.

Max.

Unit

TBIST

Duration of digital BIST

Design Information

4.8

5.15

5.5

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