L5965 datasheet(53/73 Pages) STMICROELECTRONICS

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Step

Description

Action

SPI Frame

Read

OTP

In this step, read the selected

row of OTP

Send read command and address of selected row of OTP.

Write register SAF_REG_OP=“0x002[row_addr]” via SPI

DI frame:

Bit31=’1’, bit30~23 =“0x30”,

Bit22=’1’, bit21=’1’,

bit20~11=“0x000”,

Bit10~9=”10”,

Bit8~5=”row_addr”,

bit4~0=CRC.

Read register SAF_REG_STAT via SPI. For first reading,

don’t care DO frame.

Get read back data on next DO frame, and then check if

reading operation is finished (saf_busy=0) and crc of OTP is

ok (saf_crc_ok=1/ status_crc_glb=1).

DI frame:

Bit31=’0’, bit30~23 =“0x34”,

Bit22=’1’, bit21=’0’, bit20~5=”--”,

bit4~0=CRC.

Read register SAF_REG_DO_Bit_Ts via SPI. For first reading,

don’t care DO frame.

DI frame:

Bit31=’0’, bit30~23 =“0x33”,

Bit22=’1’, bit21=’1’, bit20~5=”--”,

bit4~0=CRC.

DO frame (read back data of

SAF_REG_STAT):

Check if bit28~21=“0x34”,

If bit9=’0’, if bit8=’1’, if bit7=’1’.

Read register SAF_REG_DO_Bit_Ts via SPI again, then get

the read back data of this register on DO frame.

Note: bit15~13 of this register is crc of data1, it needs to be

checked.

DI frame:

Bit31=’0’, bit30~23 =“0x33”,

Bit22=’1’, bit21=’0’, bit20~5=”--”,

bit4~0=CRC.

DO frame:

Check if bit28~21=“0x33”,

If bit20~5=”“data1”.

6.8

OTP bit mapping and register configuration

Figure 27. OTP bit mapping

2 1 0

OTP_WD_REC_en

EnBUCK4

EnBUCK3

OvRst EN

EnLDO EnBOOST

BOOST CFG

EnVREF

CRC

BUCK3 CFG

WDG CFG

SeqId VREF

SeqId BOOST

SeqId BUCK3

SeqId LDO

USR Area Protection

Reset activation

Device identification

BUCK1 CFG

Non Prim SeqId

BUCK2 CFG

BUCK4 CFG

LDO CFG

PowrOn Delay

VREF CFG

CRC

Prim Id

SeqId BUCK4

CRC

GADG1505180950PS

Table 14. Reset activation OTP

Bit Nb

Name

Description

Row 8

Bit15:13 Reset_activation<2:0>

(1)

Reset release

000: Reset release after PGOOD of Main BUCK with a delay set by PowrOn Delay

001: Reset release after PGOOD of the 2nd regulator with a delay set by PowrOn Delay

010: Reset release after PGOOD of the 3rd regulator with a delay set by PowrOn Delay

L5965

OTP bit mapping and register configuration

DS12567 - Rev 3

page 53/73

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