L5965 datasheet(54/73 Pages) STMICROELECTRONICS

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Bit Nb

Name

Description

011: Reset release after PGOOD of the 4th regulator with a delay set by PowrOn Delay

100: Reset release after PGOOD of the 5th regulator with a delay set by PowrOn Delay

101: Reset release after PGOOD of the 6th regulator with a delay set by PowrOn Delay

110: Reset release after PGOOD of the last regulator with a delay set by PowrOn Delay

111: Reset release when ACTIVE state is reached (unconditional Reset release)

1. All regulators switched on before the Reset is released are considered part of the "Reset activation list"

Table 15. Device identification OTP

Bit Nb

Name

Description

Row 8

Bit12:7

Device_id<5:0>

Custom information. It can be read out by SPI.

Table 16. WD_REC_en OTP

Bit Nb

Name

Description

Row 8

Bit6

OTP_WD_REC_en<0>

When OTP bit = 0, SPI bit = 0 make a WD failure to assert RESET_B but not affect the FSM.

All regulators keep running in active mode. If the SPI bit = 1 WD failure asserts RESET_B

and makes FSM go to REC state.

When OTP bit = 1, a WD failure asserts RESET_B and makes FSM go to REC state.

Table 17. Buck1 CFG

Bit num

Name

Description

Row 8

Bit5:3

vsel<2:0>

Output Voltage selection

000: 5.0 V

001: 3.8 V

010: 3.3 V

011: 1.8 V

100: 1.2 V

101: 1.1 V

110: 1.0 V

111: 0.8 V

Table 18. Primary activation OTP

PrimId

Non Prim SeqId

EnBuck1

EnBuck2

Note

"101"

[001:110]

FSM=ON, SPI=CH Buck1 is primary, Buck2 is enabled by FSM

"101"

"111"

FSM=OFF,

SPI=CH

Buck1 is primary, Buck2 can be enabled by

SPI(1)

"101"

“000”

Error

"110"

[001:110]

FSM=ON SPI=CH

Buck2 is primary, Buck1 can be enabled by

FSM

"110"

“111”

FSM=OFF SPI=CH

Buck2 is primary, Buck1 can be enabled by

SPI(1)

“110”

“000”

Error

"010"

any

Buck1 is primary, Buck2 is disabled

"000 | 011 | 100 |

111"

any

Error

1. If enabled by OTP.

L5965

OTP bit mapping and register configuration

DS12567 - Rev 3

page 54/73

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