L9305EP datasheet(24/107 Pages) STMICROELECTRONICS

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•

TRANSITION TIME: Too long PWM period detection: if the current PWM time exceeds this threshold, the

controller enters the transient state. It can be programmed as follows:

–

If TRANSITION TIME = 0 →

TRANSTIME=2,5*TPWM

–

If TRANSITION TIME = 1 →

TRANSTIME=4,5*TPWM

–

If TRANSITION TIME = 2 →

TRANSTIME=8,5*TPWM

–

If TRANSITION TIME = 3 →

TRANSTIME=16,5*TPWM

6.1.6

Chopper offset compensation of current sense amplifier

This function cancels the input offset of the current sense amplifier by converting the DC input offset voltage to an

AC noise at the chopper frequency. Function is normally enabled and can be disabled by the user via SPI register

(OFS_CMP_DIS D[14] in Channel_x.CONFIGURATION1 register).

6.1.7

Staggered channel activation

Staggered channel operation is enabled by the user through the SPI Service Enable register, SERVENA (Stagger

Enable bit D[0]). When staggered operation is enabled and the targeted regulated current is achieved, the PWM

switch-on points is staggered per the following sequence:

•

Channel 0 → 0° phase advance; reference channel

•

Channel 1 → 90° phase advance

•

Channel 2 → 180° phase advance

•

Channel 3 → 270° phase advance

This function is specific to fixed frequency current control and is disabled in variable frequency mode.

6.1.8

Parallel mode

The 4 channels can be configured to work in parallel mode to allow regulation of higher current set-points: this

option is suitable for example in applications where setting HILOAD = 1 is not enough to match targets.

Channel parallelization can be enabled only for fixed channel pairs:

•

ch0 can be put in parallel with ch1 only

•

ch2 can be put in parallel with ch3 only

In parallel mode one channel acts as a master (ch0, ch2) and the other as a slave (ch1, ch3): both channel

current sense measurements are kept active to measure load current split between channel pair: the two

measurements are combined and used to close control loop on master logic only.

Configuration of parallel mode is done through master channel registers and in detail the following master

parameters are valid for both channels, overwriting slave channel configuration (if any):

•

Current set-point,

•

Dither parameters,

•

Control loop parameters (Ki, Kp, fix/var frequency mode selector, Kfi, etc…)

As a consequence of the described implementation, the resulting resolution of the current and dither set-point

registers is doubled since target value is applied on both channels in parallel: it means that in parallel mode

1 LSB = 0.5 mA instead of default 0.25 mA.

Feedback of measured average current is kept distinguished like in normal operation and available for each

channel on its own register with nominal LSB of 0.25 mA. The same applies for HS-LS compare check and

applied offset compensation.

The following parameters are kept independent between master and slave channels and particular attention must

be paid for proper configuration settings:

•

HW/SW mode selection

•

HS/LS configuration

•

INx/NDISx functionality

•

diagnostic

•

calibration data

•

offset compensation

L9305

Current control drivers

DS12774 - Rev 10

page 24/107

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