L9963E datasheet(7/184 Pages) STMICROELECTRONICS

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Pin #

Pin name

Description

I/O type(1)

VCOM

Regulated power supply used for communication interfaces. Connect a tank

capacitor as indicated in Table 73. Can be used to supply external loads with a

maximum IVCOM_ext current budget.

CGND

Communication ground. Connect to DGND on top.

ISOHp

Non-inverting, high-side isolated serial communication port. Refer to

Section 4.2.3 Isolated Serial Peripheral Interface. Refer to Section 6.8 ISO lines

circuit.

AIO

ISOHm

Inverting, high-side isolated serial communication port. Refer to

Section 4.2.3 Isolated Serial Peripheral Interface. Refer to Section 6.8 ISO lines

circuit.

AIO

DGND

Digital ground. Connect to AGND on top.

GPIO1_ FAULTH

Digital input used for FAULTH receiver. Refer to Section 4.3 FAULT line.

GPIO2_ FAULTL

Digital output used for FAULTL transmitter. Refer to Section 4.3 FAULT line.

GPIO3

General-purpose I/O. Refer to Section 4.9 General purpose I/O: GPIOs. Generally

used to sense NTCs. Refer to Section 6.9 NTC analog front end.

AI/DI/DO

GPIO4

AI/DI/DO

GPIO5

AI/DI/DO

GPIO6

AI/DI/DO

GPIO7_ WAKEUP

General-purpose I/O. Refer to Section 4.9 General purpose I/O: GPIOs. Generally

used to sense NTCs. Refer to Section 6.9 NTC analog front end. Can be

configured to act as wake up input. Refer to Section 4.9.4 GPIO7: wake up feature.

AI/DI/DO

NPNDRV

Internal voltage regulator controller output. Connect to the base of the external NPN

transistor.

VREG

Regulated analog power supply for core circuitry. Connect a tank capacitor as

indicated in Table 73. It is disabled in low power modes (Silent Balancing, Sleep

and during the OFF phase of Cyclic Wakeup). VCOM, VANA and VTREF regulators

are fed by pre-regulated VREG.

VTREF

Buffered, precise analog reference voltage for driving multiple NTCs. Connect a tank

capacitor as indicated in Table 73. It has a maximum IVTREF_ext current budget.

SPIEN

At first power up, after VCOM is out of undervoltage, this pin is sampled to

determine port L configuration. Connect to VCOM to configure SPI mode. Connect

to AGND to select isolated SPI communication.

If left floating, this pin has a 100KΩ internal Pull down, forcing isolated SPI mode.

VANA

Precise ADC analog supply. Connect a tank capacitor as indicated in Table 73.

AGND

Analog/ESD ground. Ground supply of chip.

ISENSEp

Non-inverting input of current measurement. Refer to Table 73.

ISENSEm

Inverting input of current measurement. Refer to Table 73.

GNDREF

Analog/reference GND. Connect to AGND on top

Connect to the negative terminal of 1st cell.

Cell voltage input. Connect to the positive terminal of 1st cell.

Cell balancing FET control output for 1st cell.

B2_1

Common terminal for cell balancing S1 and S2.

Cell balancing FET control output for 2nd cell.

Cell voltage input. Connect to the positive terminal of 2nd cell.

Cell voltage input. Connect to the positive terminal of 3rd cell.

Cell balancing FET control output for 3rd cell.

B4_3

Common terminal for cell balancing S3 and S4.

Cell balancing FET control output for 4th cell.

L9963E

Pin description

DS13636 - Rev 12

page 7/184

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