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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DP83867CSRGZ 데이터시트(PDF) 85 Page - Texas Instruments |
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DP83867CSRGZ 데이터시트(HTML) 85 Page - Texas Instruments |
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85 / 129 page  7.6.51 Enable Control of Receiver's Equalizer (ECRE) Table 7-61. Enable Control of Receiver's Equalizer (ECRE), Address 0x00C0 BIT BIT NAME DEFAULT DESCRIPTION 15:0 EN_CTRL_REC_EQ 0x0000, RW Enable control of receiver's equalizer. Value 0x0000 can further improve the immunity margins during EMC testing. 7.6.52 PLL Clock-out Control Register (PLLCTL) Table 7-62. PLL Clock-out Control Register (PLLCTL), Address 0x00C6 BIT BIT NAME DEFAULT DESCRIPTION 15:5 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 4 CLK_MUX 0, RW Internal Clock MUX Control: 1 = Configures analog CLK_OUT to be TX_TCLK for compliance testing. 0 = Normal operation. 3:0 RESERVED 0, RO RESERVED: Writes ignored, read as 0. www.ti.com DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: DP83867CS DP83867IS DP83867E |
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