DP83867CSRGZ datasheet(95/129 Pages) TI2

95 / 129 page

Table 7-114. I/O Configuration (IO_MUX_CFG), Address 0x0170 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

12:8

CLK_O_SEL

0 1100, RW

Clock Output Select:

01101 - 11111: RESERVED

01100: Reference clock (synchronous to XI input clock)

01011: Channel D transmit clock

01010: Channel C transmit clock

01001: Channel B transmit clock

01000: Channel A transmit clock

00111: Channel D receive clock divided by 5

00110: Channel C receive clock divided by 5

00101: Channel B receive clock divided by 5

00100: Channel A receive clock divided by 5

00011: Channel D receive clock

00010: Channel C receive clock

00001: Channel B receive clock

00000: Channel A receive clock

RESERVED

0, RO

RESERVED

CLK_O_DISABLE

0 , RW

Clock Output Disable:

1 = Disable clock output on CLK_OUT pin.

0 = Enable clock output on CLK_OUT pin.

RESERVED

0, RO

RESERVED

4:0

IO_IMPEDANCE_CTRL

TRIM, RW

Impedance Control for MAC I/Os:

Output impedance approximate range from 35-70Ω in 32 steps.

Lowest being 11111 and highest being 00000. Range and Step size

will vary with process.

Default is set to 50Ω by trim. But the default register value can

vary by process. Non default values of MAC I/O impedance can

be used based on trace impedance. Mismatch between device and

trace impedance can cause voltage overshoot and undershoot.

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DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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