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CC113LRGPR 데이터시트(PDF) 24 Page - Texas Instruments

부품명 CC113LRGPR
상세설명  CC113L Value Line Receiver
PDF  87 Pages
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제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments

CC113LRGPR 데이터시트(HTML) 24 Page - Texas Instruments

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28
DATA
DRATE _ E
XOSC
R
2
DRATE _ M
256
ƒ
2
×
=
-
×
20
DATA
2
XOSC
R
2
DRATE _ E
log
ƒ
æ
ö
×
=
ç
÷
ç
÷
è
ø
DRATE _ E
DATA
XOSC
28
(256 DRATE _ M) 2
R
ƒ
2
+
×
=
×
CC113L
SWRS108B – MAY 2011 – REVISED JUNE 2014
www.ti.com
5.7
Data Rate Programming
The data rate expected in receive mode is programmed by the MDMCFG3.DRATE_M and the
MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula
shows, the programmed data rate depends on the crystal frequency.
(1)
The following approach can be used to find suitable values for a given data rate:
(2)
(3)
If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use
DRATE_M = 0.
The data rate can be set from 0.6 kBaud to 500 kBaud with the minimum step size according to
Table 5-3. See Section 4.4 for the minimum and maximum data rates for the different modulation formats.
Table 5-3. Data Rate Step Size (Assuming a 26-MHz crystal)
Min Data Rate
Typical Data Rate
Max Data Rate
Data rate Step Size
[kBaud]
[kBaud]
[kBaud]
[kBaud]
0.6
1.0
0.79
0.0015
0.79
1.2
1.58
0.0031
1.59
2.4
3.17
0.0062
3.17
4.8
6.33
0.0124
6.35
9.6
12.7
0.0248
12.7
19.6
25.3
0.0496
25.4
38.4
50.7
0.0992
50.8
76.8
101.4
0.1984
101.6
153.6
202.8
0.3967
203.1
250
405.5
0.7935
406.3
500
500
1.5869
24
Detailed Description
Copyright © 2011–2014, Texas Instruments Incorporated
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Product Folder Links: CC113L



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