HCF1305-2R2-R datasheet(21/39 Pages) MICROCHIP

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DS20007043B-page 21

MIC24054

5.4

Ripple Injection

The VFB ripple required for proper operation of the

MIC24054 gm amplifier and error comparator is 20 mV

to 100 mV. However, the output voltage ripple is

generally designed as 1% to 2% of the output voltage.

For a low output voltage, such as a 1V, the output

voltage ripple is only 10 mV to 20 mV, and the feedback

voltage ripple is less than 20 mV. If the feedback

voltage ripple is so small that the gm amplifier and error

comparator can’t sense it, then the MIC24054 will lose

control and the output voltage is not regulated. In order

to have some amount of VFB ripple, a ripple injection

method is applied for low output voltage ripple

applications.

The applications are divided into three situations

according to the amount of the feedback voltage ripple:

1. Enough ripple at the feedback voltage due to the

large ESR of the output capacitors.

As shown in Figure 5-1, the converter is stable without

any ripple injection. The feedback voltage ripple is:

EQUATION 5-14:

FIGURE 5-1:

Enough Ripple at FB.

2. Inadequate ripple at the feedback voltage due to

the small ESR of the output capacitors.

The output voltage ripple is fed into the FB pin through

a feed-forward capacitor (CFF) in this situation, as

shown in Figure 5-2. The typical CFF value is between

1 nF and 100 nF. With the feed-forward capacitor, the

feedback voltage ripple is very close to the output

voltage ripple:

EQUATION 5-15:

FIGURE 5-2:

Inadequate Ripple at FB.

3. Virtually no ripple at the FB pin voltage due to

the very low ESR of the output capacitors.

In this situation, the output voltage ripple is less than

20 mV. Therefore, additional ripple is injected into the

FB pin from the switching node SW via a resistor Rinj

and a capacitor Cinj, as shown in Figure 5-3. The

injected ripple is:

EQUATION 5-16:

EQUATION 5-17:

FIGURE 5-3:

Invisible Ripple at FB.

In Equation 5-16 and Equation 5-17, it is assumed that

the time constant associated with CFF must be much

greater than the switching period:

EQUATION 5-18:

VFB PP







1 R2

--------------------- ESRCOUT



IL PP









Where:

ΔIL(PP) = Peak-to-peak inductor current ripple

VFB PP







ESR

IL PP











VFB PP







VIN KDIV



1 D

–







fSW 



-----------------



Where:

VIN = Power stage input voltage

D = Duty cycle

fSW = Switching frequency

τ = (R1//R2//Rinj) × CFF

KDIV

R1//R2

Rinj R1//R2

----------------------------------

fSW 



-----------------



--- 1

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