VL6624 datasheet(14/106 Pages) STMICROELECTRONICS

14 / 106 page

Operational modes

VL6624/VS6624

14/106

During the power-up sequence (CE = logic 1)

●

The digital supplies must be on and stable.

●

The internal digital supply of the VL6624/VS6624 is enabled by an internal

switch mechanism.

●

All internal registers are reset to default values by an internal power on reset

cell.

Figure 3.

Power up sequence

STANDBY mode

The VL6624/VS6624 enters STANDBY mode when the CE pin on the

device is pulled HIGH. Power consumption is very low, most clocks inside the device are

switched off.

In this state I²C communication is possible when CLK is present and when the

microprocessor is enabled.

All registers are reset to their default values. The device I/O pins have a very high-

impedance.

Uninitialised = RAW The initialize mode is defined as supplies present, the CE signal is

logic 1 and the microcontroller clock has been activated.

During initialize mode the device firmware may be patched. This state is provided as an

intermediary configuration state and is not central to regular operation of the device.

The analogue video block is powered down, leading to a lower global consumption

STOP mode

This is a low power mode. The analogue section of the

VL6624/VS6624 is switched off and all registers are accessed over the I²C interface. A run

command received in this state automatically sets a transition through the Pause state to the

run mode.

Note:

The device must be in Stop mode to adjust output size.

The analogue video block is powered down, leading to a lower global consumption.

CLK

AVDD (2.8V)

VDD (1.8V/2.8V)

SDA

SCL

t1 >= 0ns

t2 >= 0ns

t3 >= 0ns

t4 >= TBC ms

Constraints:

low level command: enable clocks

setup commands

t5 >= TBC ms

standby

POWER DOWN

uninitialised mode

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