AT25DF256 datasheet(29/47 Pages) RENESAS

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DS-AT25DF256-035 Rev.G

Page 29

2024-01-08

AT25DF256 Datasheet

12.3 Deep Power-Down

During normal operation, the device is placed in the standby mode to consume less power as long as the CS pin

remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to

place the device into an even lower power consumption state called the Deep Power-Down mode.

When the device is in the Deep Power-Down mode, all commands, including the Read Status Register command,

are ignored, with the exception of the Resume from Deep Power-Down command. Since all commands are

ignored, the mode can be used as an extra protection mechanism against program and erase operations.

Entering the Deep Power-Down mode is done by simply asserting the CS pin, clocking in the opcode of B9h, and

then deasserting the CS pin. Any additional data clocked into the device after the opcode are ignored. When the

CS pin is deasserted, the device enters the Deep Power-Down mode within the maximum time of tEDPD.

The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on

an even byte boundary (multiples of eight bits); otherwise, the device stops the operation and returns to the

standby mode once the CS pin is deasserted. Also, the device defaults to the standby mode after a power-cycle.

The Deep Power-Down command is ignored if an internally self-timed operation such as a program or erase cycle

is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has

been completed in order for the device to enter the Deep Power-Down mode.

Figure 23. Deep Power-Down

SCK

MSB

ICC

10111001

OPCODE

HIGH-IMPEDANCE

Standby Mode Current

Active Current

Deep Power-Down Mode Current

tEDPD

AT25DF256 데이터시트(PDF) 29 Page - Renesas Technology Corp