AT25DF256 datasheet(34/47 Pages) RENESAS

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DS-AT25DF256-035 Rev.G

Page 34

2024-01-08

AT25DF256 Datasheet

12.8 Reset

In some applications, it might be necessary to prematurely stop a program or erase operation rather than wait the

hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally.

The Reset command allows a program or erase operation in progress to be ended abruptly and returns the device

to an idle state. Since the need to reset the device is immediate, the Write Enable command does not need to be

issued prior to the Reset command. Thus, the Reset command operates independently of the state of the WEL bit

in the Status Register.

The Reset command can be executed only if the command has been enabled by setting the Reset Enabled

(RSTE) bit in the Status Register to a Logical 1 using write status register byte 2 command 31h. Enter this

command before a program command is entered. If the Reset command has not been enabled (the RSTE bit is in

the Logical 0 state), then any attempts at executing the Reset command are ignored.

To perform a Reset, the CS pin must first be asserted, and then the opcode F0h must be clocked into the device.

No address bytes need to be clocked in, but a confirmation byte of D0h must be clocked into the device

immediately after the opcode. Any additional data clocked into the device after the confirmation byte are ignored.

When the CS pin is deasserted, the program operation currently in progress is stopped within a time of tSWRST.

Since the program or erase operation might not complete before the device is reset, the contents of the page

being programmed or erased cannot be guaranteed to be valid.

The Reset command has no effect on the states of the Configuration Register or RSTE bit in the Status Register.

The WEL bit, however, is reset to its default state.

The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and

the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation

is done.

Figure 29. Reset

SCK

MSB

1111000

Opcode

Confirmation Byte In

10 11

814 15

MSB

1101000

High-impedance

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