AT25DF256 datasheet(33/47 Pages) RENESAS

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DS-AT25DF256-035 Rev.G

Page 33

2024-01-08

AT25DF256 Datasheet

12.7 Hold

The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock

sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a

program or erase cycle. Thus, if an erase cycle is in progress, asserting the HOLD pin does not pause the

operation, and the erase cycle continues until it is finished.

The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting

the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold

mode won’t be started until the beginning of the next SCK low pulse. The device remains in the Hold mode as long

as the HOLD pin and CS pin are asserted.

While in the Hold mode, the SO pin is in a high-impedance state. Also, both the SI pin and the SCK pin are

ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode.

To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low

pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode does not end until the

beginning of the next SCK low pulse.

If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that was started is stopped,

and the device resets the WEL bit in the Status Register to the logical 0 state.

Figure 28. Hold Mode

SCK

HOLD

Hold

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