MSC8103SLASHD datasheet(48/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

2-8

Freescale Semiconductor

Physical and Electrical Specifications

2.6.3

Clocking and Timing Characteristics

Figure 2-5.

Start-Up Sequence with CLKIN Started After VDDH and Before VDD

Figure 2-6.

Start-Up Sequence with VDDH Raised Before VDD with CLKIN Started Before VDD = 0.5 V

Table 2-10.

System Clock Parameters

Characteristic

Minimum

Maximum

Unit

Phase Jitter between BCLK and DLLIN

—

0.5

CLKIN frequency1,2

100

MHz

CLKIN slope

—

DLLIN slope

—

CLKOUT frequency jitter

—

(0.01/CLKOUT) + CLKIN jitter

Delay between CLKOUT and DLLIN

—

Notes:

Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the frequency after the

predivider (SPLLMFCLK) higher than 18 MHz.

CLKIN should have a 50%

± 5% duty cycle.

Time

3.3 V

1.6 V

VDDH Nominal

PORESET/TRST asserted

VDD Nominal

CLKIN starts toggling

VDDH applied

PORESET/TRST Deasserted

VDD applied

1.06 V

VDDH = Nominal

VDD = Nominal

Time

o.5 V

3.3 V

1.6 V

VDDH Nominal

PORESET/TRST asserted

VDD Nominal

CLKIN starts toggling

VDDH applied

PORESET/TRST deasserted

VDD applied

1.06 V

VDDH = Nominal

VDD = Nominal

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