MSC8103SLASHD datasheet(18/104 Pages) FREESCALE

18 / 104 page

MSC8103 Network Digital Signal Processor, Rev. 11

1-14

Freescale Semiconductor

Signals/Connections

PSDA10

PGPL0

Output

Bus SDRAM A10

Output from the bus SDRAM controller. This pin is part of the address when a row address is driven.

It is part of the command when a column address is driven.

Bus UPM General-Purpose Line 0

One of six general-purpose output lines of the UPM. The values and timing of this pin are

programmed in the UPM.

PSDWE

PGPL1

Output

Bus SDRAM Write Enable

Output from the bus SDRAM controller. This pin should connect to the SDRAM WE input signal.

Bus UPM General-Purpose Line 1

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

POE

PSDRAS

PGPL2

Output

Bus Output Enable

Output of the bus GPCM. Controls the output buffer of memory devices during read operations.

Bus SDRAM RAS

Output from the bus SDRAM controller. This pin should connect to the SDRAM Row Address Strobe

(RAS) input signal.

Bus UPM General-Purpose Line 2

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

PSDCAS

PGPL3

Output

Bus SDRAM CAS

Output from the bus SDRAM controller. This pin should connect to the SDRAM Column Address

Strobe (CAS) input signal.

Bus UPM General-Purpose Line 3

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

PGTA

PUPMWAIT

PPBS

PGPL4

Input

Output

GPCM TA

Terminates transactions during GPCM operation. Requires an external pull up resistor for proper

operation.

Bus UPM Wait

Input to the UPM. An external device can hold this pin high to force the UPM to wait until the device

is ready for the operation to continue.

Bus Parity Byte Select

In systems that store data parity in a separate chip, this output is the byte-select for that chip.

Bus UPM General-Purpose Line 4

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

PSDAMUX

PGPL5

Output

Bus SDRAM Address Multiplexer

Controls the SDRAM address multiplexer when the MSC8103 is in External Master mode.

Bus UPM General-Purpose Line 5

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

Table 1-6.

Memory Controller Signals (Continued)

Signal

Data Flow

Description

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