MSC8103SLASHD datasheet(19/104 Pages) FREESCALE

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CPM Ports

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

1-15

1.6 CPM Ports

The MSC8103 CPM supports the subset of MPC8260 signals as described below.

• The MSC8103 CPM includes the following set of communication controllers:

• Two full-duplex fast serial communications controllers (FCCs) that support:

— Asynchronous transfer mode (ATM) through a UTOPIA 8 interface (FCC1 only)—The MSC8103 can

operate as one of the following:

° UTOPIA slave device

° UTOPIA multi-PHY master device using direct polling for up to 4 PHY devices

° UTOPIA multi-PHY master device using multiplex polling that can address up to 31 PHY devices at addresses 0–30

(address 31 is reserved as a null port).

— IEEE 802.3/Fast Ethernet through a Media-Independent Interface (MII)

— High-level data link control (HDLC) Protocol:

° Serial mode—Transfers data one bit at a time

° Nibble mode—Transfers data four bits at a time

— Transparent mode serial operation

• One FCC that operates with the TSA only

• Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64

Kbps each, multiplexed on up to four TDM interfaces

• Two full-duplex serial communications controllers (SCCs) that support the following protocols:

— IEEE 802.3/fast Ethernet through a media-independent interface (MII)

— HDLC Protocol:

° Serial mode—Transfers data one bit at a time

° Nibble mode—Transfers data four bits at a time

— Synchronous data link control (SDLC)

— LocalTalk (HDLC-based local area network protocol)

— Universal asynchronous receiver/transmitter (UART)

— Synchronous UART (1x clock mode)

— Binary synchronous (BISYNC) communication

— Transparent mode serial operation

• Two additional SCCs that operate with the TSA only

• Two full-duplex serial management controllers (SMCs) that support the following protocols:

— General circuit interface (GCI)/integrated services digital network (ISDN) monitor and C/I channels (TSA

only)

— UART

— Transparent mode serial operation

• Serial peripheral interface (SPI) support for master or slave operation

• Inter-integrated circuit (I2C) bus controller

• Time-slot assigner (TSA) that supports multiplexing from any of the SCCs, FCCs, SMCs, and two MCCs onto

four time-division multiplexed (TDM) interfaces. The TSA uses two serial interfaces (SI1 and SI2). SI1 uses

TDMA1 which supports both serial and nibble mode. SI2 does not support nibble mode and includes TDMB2,

TDMC2, and TDMD2, which operate only in serial mode.

The individual sets of externals signals associated with a specific protocol and data transfer mode are multiplexed

across any or all of the ports, as shown in Figure 1-2. The following sections describe the signals supported by

Ports A–D.

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