MSC8103SLASHD datasheet(54/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

2-14

Freescale Semiconductor

Physical and Electrical Specifications

2.6.5

System Bus Access Timing

2.6.5.1 Core Data Transfers

Generally, all MSC8103 bus and system output signals are driven from the rising edge of the reference clock

(REFCLK), which is DLLIN. Memory controller signals, however, trigger on four points within a DLLIN cycle.

Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of DLLIN (and

T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 2-15 shows.

Figure 2-9 is a graphical representation of Table 2-15.

Note:

The UPM machine and GPCM machine outputs change on the internal tick determined by the memory

controller programming; the AC specifications are relative to the internal tick. SDRAM machine outputs

change only on the DLLIN rising edge.

Table 2-15.

Tick Spacing for Memory Controller Signals

PLL Clock Ratio

Tick Spacing (T1 Occurs at the Rising Edge of DLLIN)

1:2, 1:3, 1:4, 1:5, 1:6

1/4 DLLIN

1/2 DLLIN

3/4 DLLIN

1:2.5

3/10 DLLIN

1/2 DLLIN

8/10 DLLIN

1:3.5

4/14 DLLIN

1/2 DLLIN

11/14 DLLIN

Figure 2-9.

Internal Tick Spacing for Memory Controller Signals

DLLIN

for 1:2.5

for 1:3.5

DLLIN

for 1:2, 1:3, 1:4, 1:5, 1:6

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