M48T129Y, M48T129V

4/22

Note: 1. For pin connections, see individual data sheets for M48T201Y/V and M68Z128/W at www.st.com.

2. For 5V, M48T129Y (M48T201Y + M68Z128). For 3.3V, M48T129V (M48T201V + M68Z128W).

3. SNAPHAT Top ordered separately.

AI03632

32,768 Hz

CRYSTAL

LITHIUM

CELL

A0-A16

DQ0-DQ7

E

VCC

W

G

WDI

RSTIN1

RSTIN2

VSS

E

W

G

VCC

VSS

A0-A16

DQ0-DQ7

0.1

µF

0.1

µF

5V

ECON

GCON

RST

IRQ/FT

SQW

M48T201Y/V

(2)

M68Z128/W

(2)

VOUT

BATTERY/CRYSTAL

READ MODE

The M48T129Y/V is in the Read Mode whenever

W (Write Enable) is high and E (Chip Enable) is

low. The unique address specified by the 17 Ad-

dress Inputs defines which one of the 131,072

bytes of data is to be accessed. Valid data will be

dress Access Time) after the last address input

signal is stable, providing the E and G access

times are also satisfied. If the E and G access

times are not met, valid data will be available after

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

puts are changed while E and G remain active,

Data Hold Time) but will go indeterminate until the

next Address Access.

WRITE MODE

The M48T129Y/V is in the Write Mode whenever

W (Write Enable) and E (Chip Enable) are low

state after the address inputs are stable.

The start of a write is referenced from the latter oc-

curring falling edge of W or E. A write is terminated

by the earlier rising edge of W or E. The addresses

must be held valid throughout the cycle. E or W

tiation of another read or write cycle. Data-in must

during write cycles to avoid bus contention; al-

though, if the output bus has been activated by a

low on E and G a low on W will disable the outputs