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M48T129Y, M48T129V

Table 4. AC Measurement Conditions

Note that Output Hi-Z is defined as the point where data is no longer

driven.

Input Rise and Fall Times

≤ 5ns

Input Pulse Voltages

0 to 3V

Input and Output Timing Ref. Voltages

1.5V

Figure 5. AC Testing Load Circuit

Note: Excluding open drain output pins

AI01803C

CL = 100pF

CL includes JIG capacitance

650

Ω

DEVICE

UNDER

TEST

1.75V

2. See Table 7 for details.

Mode

E

G

W

DQ0-DQ7

Power

Deselect

4.5V to 5.5V

or

3.0V to 3.6V

X

X

High Z

Standby

Write

X

Active

Read

Active

Read

High Z

Active

Deselect

(2)

X

X

X

High Z

CMOS Standby

Deselect

X

X

X

High Z

Battery Back-up Mode

external copies are independent of internal func-

tions except that they are updated periodically by

the simultaneous transfer of the incremented inter-

nal copy. TIMEKEEPER and Alarm Registers

store data in BCD.

DATA RETENTION MODE

as a conventional BYTEWIDE

™ static RAM.

Should the supply voltage decay, the RAM will au-

tomatically deselect, write protecting itself when

dow. All outputs become high impedance and all

inputs are treated as ”don’t care”.

Note: A power failure during a write cycle may cor-

rupt data at the current addressed location, but

does not jeopardize the rest of the RAM’s content.

into the deselect window during the time the de-

power supply lines is recommended.

switches power to the internal battery, preserving

data and powering the clock. The internal energy

source will maintain data in the M48T129Y/V for

an accumulated period of at least 10 years at room

the battery is disconnected, and the power supply

more detailed review of lifetime calculations,

please see Application Note AN1012.

TIMEKEEPER REGISTERS

The M48T129Y/V offers 16 internal registers

which contain TIMEKEEPER, Alarm, Watchdog,

Interrupt, Flag, and Control data. These registers

are memory locations which contain external (user

accessible) and internal copies of the data (usually

referred to as BiPORT TIMEKEEPER cells). The