L6711 datasheet(19/50 Pages) STMICROELECTRONICS

19 / 50 page

L6711

Current reading and current sharing control loop

19/50

Current reading and current sharing control loop

The device embeds a flexible, fully-differential current sense circuitry that is able to read

across both low side or inductor parasitic resistance or across a sense resistor placed in

series to that element. The fully-differential current reading rejects noise and allows placing

sensing element in different locations without affecting the measurement's accuracy. The

kind of sense element can be simply chosen through the CS_SEL pin: setting this pin free,

the LS mosfet is used while shorting it to SGND, the inductor will be used instead. Details

about connections are shown in Figure 5.

The high bandwidth current sharing control loop allows current balance even during load

transients: a current reference equal to the average of the read current (IAVG) is internally

built and the error between the read current and this reference is converted to a voltage that

with a proper gain is used to adjust the duty cycle whose dominant value is set by the

voltage error amplifier.

Figure 5.

Current reading connections selectable through CS_SEL pin.

7.1

Low-side current reading

Leaving CS_SEL pin OPEN, the current flowing trough each phase is read using the voltage

drop across the low side mosfets RdsON or across a sense resistor in its series and it is

internally converted into a current. The transconductance ratio is issued by the external

resistor Rg placed outside the chip between CSx- and CSx+ pins toward the reading points

(see Figure 6 right). The proprietary current sense circuit tracks the current information for a

time TTRACK = TSW/3 (TSW = 1/FSW) centered in the middle of the low-side mosfet

conduction time (OFF Time, see Figure 6 left) and holds the tracked information during the

rest of the period.

This device sources a constant 50

µA current from the CSx+ pin: the current reading circuitry

uses this pin as a reference and the reaction keeps the CSx- pin to this voltage during the

reading time (an internal clamp keeps CSx+ and CSx- at the same voltage sinking from the

CSx- pin the necessary current during the hold time; this is needed when LS mosfet RdsON

sense is implemented to avoid absolute maximum rating overcome on CSx- pin). The

current that flows from the CSx- pin is then given by the following equation (See Figure 6 -

right):

where:

RdsON is the on resistance of the low side mosfet and Rg is the transconductance resistor

used between CSx- and CSx+ pins toward the reading points; IPHASEx is the current carried

by the relative phase and IINFOx is the current information signal reproduced internally.

Rg(RC)

CSx+

CSx-

PHASEx

OUT

IPHASE

CS_SEL

Rg(a)

LS MOSFET Current Sense

Inductor Current Sense

CSx-

CSx+

LGATEx

IPHASE

CS_SEL

CSx-

µA

dsON

----------------- IPHASEx

⋅

µAI

INFOx

dsON

----------------- IPHASEx

⋅

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