R7FA6T2AB3CFM datasheet(32/101 Pages) RENESAS

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2.3.3

Reset Timing

Table 2.17

Reset timing

Parameter

Symbol Min Typ Max

Unit Test conditions

RES pulse width

Power-on

tRESWP 0.7 —

—

Figure 2.7

Deep Software Standby mode

tRESWD 0.6 —

—

Figure 2.8

Software Standby mode

tRESWS 0.3 —

—

All other

tRESW

200 —

—

µs

Wait time after RES cancellation

tRESWT —

37.3 41.2

µs

Figure 2.7

Wait time after internal reset cancellation

(IWDT reset, WDT reset, software reset, SRAM parity error reset, bus master MPU

error reset, TrustZone error reset, Cache parity error reset)

tRESW2 —

324 397.7 µs

—

VCC

RES

Internal reset signal

(low is valid)

tRESWP

tRESWT

VCCmin

Figure 2.7

RES pin input timing under the condition that VCC exceeds VPOR voltage threshold

RES

Internal reset signal

(low is valid)

tRESWD, tRESWS, tRESW

tRESWT

Figure 2.8

Reset input timing

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0150 Rev.1.50

Jul 2, 2025

Page 32 of 101

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