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R7FA6T2AB3CFM 데이터시트(PDF) 6 Page - Renesas Technology Corp |
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R7FA6T2AB3CFM 데이터시트(HTML) 6 Page - Renesas Technology Corp |
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6 / 101 page ![]() 1.2 Block Diagram Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the features. Memory 512 KB code flash 16 KB data flash 64 KB SRAM DMA DMAC × 8 System Mode control Power control Register write protection MOSC Clocks (H/M/L) OCO PLL/PLL2 Arm Cortex-M33 DTC CAC POR/LVD Reset ELC Event link SCE5 Security Analog Data processing Communication interfaces IIC × 2 SPI × 2 CANFD × 1 SCI × 6 TSN DAC12 × 4 ADC × 2 with PGA 1 KB Standby SRAM ICU MPU NVIC System timer Test and DBG interface IDAU DSP FPU KINT ACMPHS Timers AGT × 2 WDT/IWDT TFU Data processing accelerator IIRFA Bus MPU CRC DOC PDG × 4 GPT × 10 Note: Not available on all parts. Figure 1.1 Block diagram 1.3 Part Numbering Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.11 shows a list of products. RA6T2 Datasheet 1. Overview R01DS0400EJ0150 Rev.1.50 Jul 2, 2025 Page 6 of 101 |
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