R7KA8M2AFDCAM datasheet(255/295 Pages) RENESAS

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Note:

These specification values are applicable when only one ADC16H is operating, DAC12 and ACMPHS are not operating, and there

is no access to the external bus during A/D conversion.

If other ADC unit, DAC12, or ACMPHS is operating or bus access occurs during A/D conversion, values might not fall within the

indicated ranges.

The use of ports 0 as digital outputs is not allowed when the ADC16H is used.

The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and ADC16H input voltage is stable.

Note 1. Channel-dedicated sample-and-hold circuits are not available in these channels.

Note 2. Test conditions: 0.2% to 99.8% of the analog input voltage range.

Note 3. DNL is measured using the Histogram Method, so the lower limit value is -1.

Note 4. This value is based on a 12-bit resolution.

Table 2.103

A/D conversion characteristics (Hybrid mode)

Conditions: AVCC: 1.62 to 2.7 V, VCC: 1.62 to 2.7 V, VREFH0/VREFH: 1.62 V to AVCC

Parameter

Min

Typ

Max

Unit

Test conditions

Hybrid

mode

Without

channel

dedicated

sample and

hold circuits

Single-

ended

input

High-speed channels

(AN000 to AN005)

(AN006 to AN011)

Offset error *3

—

±0.5

±4

LSB

● ADCLK: 50 MHz

● Sampling time: 40 ADCLK

● Successive approximation time:

10 ADCLK

● Signal source impedance: 50 Ω or

less

● Digital filter: Sinc filter

Gain error *3

—

±1

±5

LSB

DNL differential

nonlinearity

error*1 *2

—

-1 to

+2.5

LSB

INL integral

nonlinearity

error*1

—

±4

±8

LSB

Middle-speed

channels (AN012 to

AN015)

Offset error *3

—

±0.5

±4

LSB

● ADCLK: 50 MHz

● Sampling time: 60 ADCLK

● Successive approximation time:

10 ADCLK

● Signal source impedance: 50 Ω or

less

● Digital filter: Sinc filter

Gain error *3

—

±1

±5

LSB

DNL differential

nonlinearity

error*1 *2

—

-1 to

LSB

INL integral

nonlinearity

error*1

—

±4

±8

LSB

Low-speed channels

(AN016 to AN022)

Offset error *3

—

±0.5

±4

LSB

● ADCLK: 50 MHz

● Sampling time: 84 ADCLK

● Successive approximation time:

10 ADCLK

● Signal source impedance: 50 Ω or

less

● Digital filter: Sinc filter

Gain error*3

—

±1

±5

LSB

DNL differential

nonlinearity

error*1 *2

—

-1 to

LSB

INL integral

nonlinearity

error*1

—

±4

±12

LSB

Differenti

al input

High-speed channels

(AN000 to AN005)

(AN006 to AN011)

Offset error *3

—

±0.25

±2

LSB

● ADCLK: 50 MHz

● Sampling time: 40 ADCLK

● Successive approximation time:

10 ADCLK

● Signal source impedance: 50 Ω or

less

● Digital filter: Sinc filter

Gain error *3

—

±0.5

±2.5

LSB

DNL differential

nonlinearity

error*1 *2

—

-1 to

+2.5

LSB

INL integral

nonlinearity

error*1

—

±3

±6

LSB

Note:

These specification values are applicable when only one ADC16H is operating, DAC12 and ACMPHS are not operating, and there

is no access to the external bus during A/D conversion.

If other ADC unit, DAC12, or ACMPHS is operating or bus access occurs during A/D conversion, values might not fall within the

indicated ranges.

The use of ports 0 as digital outputs is not allowed when the ADC16H is used.

The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and ADC16H input voltage is stable.

Note 1. Test conditions: 0.2% to 99.8% of the analog input voltage range.

Note 2. DNL is measured using the Histogram Method, so the lower limit value is -1.

Note 3. This value is based on a 12-bit resolution.

Table 2.104

A/D internal reference voltage characteristics (1 of 2)

Parameter

Min

Typ

Max

Unit

Test conditions

A/D internal

reference voltage

0.77

0.8

0.84

—

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 255 of 295

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