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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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R7KA8M2AFDCAM 데이터시트(PDF) 259 Page - Renesas Technology Corp |
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R7KA8M2AFDCAM 데이터시트(HTML) 259 Page - Renesas Technology Corp |
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259 / 295 page  Table 2.110 Power-on reset circuit and voltage detection circuit characteristics (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions Internal reset time*1 Power-on reset time tPOR1 — — 6.7 ms Figure 2.139 tPOR2 — — 1.6 PVD0 reset time tPVD0 — — *1 Figure 2.139 PVD1 reset time tPVD1 — — *1 Figure 2.140 PVD2 reset time tPVD2 — — *1 PVD4 reset time tPVD4 — — *1 PVD5 reset time tPVD5 — — *1 Minimum VCC downtime (POR)*2 50mV < VD tVOFFP 900 — — µs Figure 2.139 VD ≤ 50mV 2000 — — Minimum VCC downtime (PVD)*2 PVD0 tVOFF 25 — — µs Figure 2.140 PVD1, PVD2, PVD4, PVD5 25 — — Response delay time (POR) 50mV < VD tdetp — — 900 µs Figure 2.139 VD ≤ 50mV — — 2000 Response delay time (PVD) PVD0 tdet — — 25 µs Figure 2.140, Figure 2.141 PVD1, PVD2, PVD4, PVD5 — — 25 PVDn operation stabilization time (after PVD is enabled) (n = 1, 2, 4, 5) Td (E−A) — — 20 µs Figure 2.141 Note 1. The maximum value of tPVD0, tPVD1, tPVD2, tPVD4, tPVD5 are equal to tDSBY because the internal reset time is maximized when returning from Deep Software Standby mode. Note 2. The minimum VCC downtime indicates the time when VCC is below the minimum value of voltage detection levels VPOR1, Vdet0, Vdet1, Vdet2, Vdet4 and Vdet5 for the POR / PVD. Internal reset signal (Low is valid) VCC tVOFFP tPOR2 VPOR2 VPOR1 tPOR1 tPOR *1 tPOR2 VPOR2 VPOR1 tPOR1 [slow power-on case] [fast power-on case] tdetp tPOR2 tPOR1 tVOFFP tdetp tPOR1 tVOFFP tdetp tPOR2 tPOR1 tPOR *1 tPOR *1 tPOR *1 tPOR *1 VD VD VD Note 1. tPOR is determined by the earlier point in time when the tPOR1 has passed after crossing VPOR1 or when the tPOR2 has passed after crossing VPOR2. Figure 2.139 Power-on reset timing RA8M2 Datasheet 2. Electrical Characteristics R01DS0438EJ0130 Rev.1.30 Feb 27, 2026 Page 259 of 295 |
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