R7KA8M2AFECAC datasheet(57/295 Pages) RENESAS

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Table 2.8

Current of high-speed mode, maximum condition (MVE and peripheral operation) (DCDC

mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C 125 °C

Supply

current

*1 *2*6

—

ICC

3.85

6.27

6.69

8.01

—

CPUC

LK0 =

1 GHz

CPUC

LK1 =

250

MHz

VSCR_

VCC_DCD

C ≥ 2.5 V

ICC_DCDC *4 176

340

—

VCC_DCDC = 3.3 V

MRICLK = 250 MHz, MRPCLK = 125 MHz,

ICLK = 250 MHz, BCLK = 125 MHz, PCLKA

= 125 MHz, PCLKB = 62.5 MHz, PCLKC =

125 MHz, PCLKD = 250 MHz, PCLKE = 250

MHz

IDD *3

452

873

—

VCC_DCD

C < 2.5 V

ICC_DCDC *4 343

664

—

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

452

873

—

CPUC

LK0 =

800

MHz

CPUC

LK1 =

200

MHz

VSCR_

VCC_DCD

C ≥ 2.5 V

ICC_DCDC *4 148

—

356

—

VCC_DCDC = 3.3 V

MRICLK = 200 MHz, MRPCLK = 100 MHz,

ICLK = 200 MHz, BCLK = 100 MHz, PCLKA

= 100 MHz, PCLKB = 50 MHz, PCLKC =

100 MHz, PCLKD = 200 MHz, PCLKE = 200

MHz

IDD *3

380

—

915

—

VCC_DCD

C < 2.5 V

ICC_DCDC *4 289

—

696

—

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

380

—

915

—

CPUC

LK0 =

600

MHz

CPUC

LK1 =

200

MHz

VSCR_

VCC_DCD

C ≥ 2.5 V

ICC_DCDC *4 129

—

390

VCC_DCDC = 3.3 V

MRICLK = 200 MHz, MRPCLK = 100 MHz,

ICLK = 200 MHz, BCLK = 100 MHz, PCLKA

= 100 MHz, PCLKB = 50 MHz, PCLKC =

100 MHz, PCLKD = 200 MHz, PCLKE = 200

MHz

IDD *3

330

—

1000 *5

VCC_DCD

C < 2.5 V

ICC_DCDC *4 251

—

760

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

330

—

1000 *5

CPUC

LK0 =

600

MHz

CPUC

LK1 =

150

MHz

VSCR_

VCC_DCD

C ≥ 2.5 V

ICC_DCDC *4 115

282

309

366

VCC_DCDC = 3.3 V

MRICLK = 150 MHz, MRPCLK = 75 MHz,

ICLK = 150 MHz, BCLK = 75 MHz, PCLKA

= 75 MHz, PCLKB = 37.5 MHz, PCLKC =

75 MHz, PCLKD = 150 MHz, PCLKE = 150

MHz

IDD *3

301

738

810

959

VCC_DCD

C < 2.5 V

ICC_DCDC *4 224

550

604

715

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

301

738

810

959

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Measured with clocks supplied to the peripheral functions and peripherals being operated. This does not include the BGO

operation.

Note 3. IDD depends on f (CPUCLK0 and ICLK) as follows. The ICLK items in the formula include CPU1 current.

IDD Typ. = 0.25 × fCPUCLK0 + 0.77 × fICLK + 21 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 95℃) = 0.22 × fCPUCLK0 + 0.80 × fICLK + 477 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 105℃) = 0.22 × fCPUCLK0 + 0.80 × fICLK + 553 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 125℃) = 0.22 × fCPUCLK0 + 0.80 × fICLK + 709 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 95℃) = 0.22 × fCPUCLK0 + 0.93 × fICLK + 464 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 105℃) = 0.22 × fCPUCLK0 + 0.93 × fICLK + 537 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 125℃) = 0.22 × fCPUCLK0 + 0.93 × fICLK + 691 (unit : mA, fCPUCLK0 and fICLK are MHz)

Note 4. Typical DCDC efficiency and the voltage of the test conditions are applied.

Note 5. Do not let actual consumption current during operation exceed the current value described here.

Note 6. The power consumption is calculated as Power = VCC × Icc + VCC_DCDC × Icc_DCDC.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 57 of 295

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