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tDr, tDf

tSA

tOH

tLEAD

tTD

tLAG

LSB OUT

(Last data)

DATA

MSB OUT

MSB IN

DATA

LSB IN

MSB IN

LSB OUT

tSU

tOD

tREL

MSB OUT

SSn

input

SCKn

CPOL = 1

input

SCKn

CPOL = 0

input

MISOn

output

MOSIn

input

Note:

n = 0 to 4, 9

Figure 2.73

SCI simple SPI mode timing for slave when CPHA = 1

Table 2.62

SCI timing (Simple IIC mode)

Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

VCC/VCC2 : 1.62 V or above

If SCI pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC = VCC2.

Parameter

Symbol

Min

Max

Unit

Note

Simple IIC

(Standard mode)

SCL, SDA input rise time

tSr

—

1000

SCL, SDA input fall time

tSf

—

300

SCL, SDA input spike pulse removal

time

tSP

4 × tTcyc

Data input setup time

tSDAS

250

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*1

—

400

Simple IIC (Fast

mode)

SCL, SDA input rise time

tSr

—

300

SCL, SDA input fall time

tSf

—

300

SCL, SDA input spike pulse removal

time

tSP

4 × tTcyc

Data input setup time

tSDAS

100

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*1

—

400

Note:

tTcyc: TCLK cycle.

Note 1. Cb indicates the total capacity of the bus line.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 162 of 295

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