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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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R7KA8M2AFECAC 데이터시트(PDF) 204 Page - Renesas Technology Corp |
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R7KA8M2AFECAC 데이터시트(HTML) 204 Page - Renesas Technology Corp |
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204 / 295 page  PIN1 PIN2 0.7×VCC 0.3×VCC 0.7×VCC 0.3×VCC tSKEW tEDGE_MAX tMASK tEDGE_MIN PIN1 & PIN2 tCLOCK 0.7×VCC 0.3×VCC MASK tEYE max MASK tEYE min MASK PIN1 & PIN2 0.7×VCC 0.3×VCC MAX EYE Opening MIN EYE Opening Design Conditions 1. The The differences of load magnitude and drive strength between the SDA and SCL lines result in different slopes, as shown 2. MASK period ≧ MAX tSKEW + MAX rise/fall time between 0.3 × VDD and 0.7 × VDD, respectively, decreased by the time crossing the hysteresis window. Simplifying Assumptions 1. tSKEW is the same for both edges 2. Base CLOCK (e.g. 12.5MHz) is asymmetrical 3. Falling edges are equal rising edges 4. The MASK is shown as starting, from the last possible moment, whereas in reality it could be shifted left (towards the start point) delayed by the hysteresis window Figure 2.101 Ternary Protocol Timing RA8M2 Datasheet 2. Electrical Characteristics R01DS0438EJ0130 Rev.1.30 Feb 27, 2026 Page 204 of 295 |
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