PSD4235G2 datasheet(64/89 Pages) STMICROELECTRONICS

64 / 89 page

PSD4235G2

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JTAG Extensions. TSTAT and TERR are two

JTAG extension signals enabled by a JTAG com-

mand received over the four standard JTAG pins

(TMS, TCK, TDI, and TDO). They are used to

speed Program and Erase cycles by indicating

status on PSD pins instead of having to scan the

status out serially using the standard JTAG chan-

nel. See Application Note

AN1153.

TERR indicates if an error has occurred when

erasing a sector or programming in Flash memory.

This signal goes Low (active) when an Error con-

dition occurs, and stays Low until a specific JTAG

command is executed or a Reset (RESET) pulse

is received after an “ISC_DISABLE” command.

TSTAT behaves the same as Ready/Busy (PE4)

described in the section entitled “Ready/Busy

(PE4)”, on page 21. TSTAT is High when the

PSD4235G2 device is in Read mode (primary

Flash memory and secondary Flash memory con-

tents can be read). TSTAT is Low when Flash

memory Program or Erase cycles are in progress,

and also when data is being written to the second-

ary Flash memory .

TSTAT and TERR can be configured as open-

drain type signals with a JTAG command.

Note: The state of Reset (Reset) does not interrupt

(or prevent) JTAG operations if the JTAG signals

are dedicated by an NVM Configuration bit (via

PSDsoft Express). However, Reset (Reset) pre-

vents or interrupts JTAG operations if the JTAG

Enable Register (as shown in Table 21) is used to

enable the JTAG signals.

Security and Flash memory Protection. When

the security bit is set, the device cannot be read on

a Device Programmer or through the JTAG Port.

When using the JTAG Port, only a Full Chip Erase

command is allowed.

All other Program, Erase and Verify commands

are blocked. Full Chip Erase returns the device to

a non-secured blank state. The Security Bit can be

set in PSDsoft Express.

All primary Flash memory and secondary Flash

memory sectors can individually be sector protect-

ed against erasure. The sector protect bits can be

set in PSDsoft Express.

INITIAL DELIVERY STATE

When delivered from ST, the PSD device has all

bits in the memory and PLDs set to 1. The PSD

Configuration Register bits are set to 0. The code,

configuration, and PLD logic are loaded using the

programming procedure. Information for program-

ming the device is available directly from ST.

Please contact your local sales representative.

PE4

TSTAT

Status

PE5

TERR

Error Flag

Port E Pin

JTAG Signals

Description

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