PSD4235G2 datasheet(52/89 Pages) STMICROELECTRONICS

52 / 89 page

PSD4235G2

52/89

Table 39. Port Operating Modes

Note: 1. Can be multiplexed with other I/O functions.

2. Available to Motorola 16-bit 683xx and HC16 families of MCUs.

Table 40. Port Operating Mode Settings

Note: 1. N/A = Not Applicable

2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array.

3. Any of these three methods enables the JTAG pins on Port E.

4. Control Register setting is not applicable to Ports A, B and C.

Port Mode

Port A

Port B

Port C

Port D

Port E

Port F

Port G

MCU I/O

Yes

PLD I/O

McellA Outputs

McellB Outputs

Additional Ext. CS Outputs

PLD Inputs

Yes

Address Out

Yes (A7 – 0)

or (A15 – 8)

Address In

Yes

Data Port

Yes

Peripheral I/O

Yes

JTAG ISP

Yes1

MCU Reset Mode2

Yes

Mode

Defined in PSDsoft

Express

Control

Setting

Direction

Setting

VM Register

Setting

JTAG Enable

MCU I/O

Declare pins only

0 (Note 4)

1 = output,

0 = input

(Note 2)

N/A

PLD I/O

Declare pins and

Logic equations

N/A

(Note 2)

N/A

Data Port (Port F, G)

Selected for MCU

with non-multiplexed

bus

N/A

Address Out

(Port E, F, G)

Declare pins only

1 (Note 2)

N/A

Address In

(Port A, B, C, D, F)

Declare pins or Logic

equation for Input

Macrocells

N/A

Peripheral I/O

(Port F)

Logic equations

(PSEL0 and PSEL1)

N/A

PIO bit = 1

N/A

JTAG ISP 3

Declare pins only

N/A

JTAG_Enable

MCU Reset Mode

Specific pin logic level N/A

N/A

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