PSD4235G2 datasheet(50/89 Pages) STMICROELECTRONICS

50 / 89 page

PSD4235G2

50/89

I/O PORTS

There are seven programmable I/O ports: Ports A,

B, C, D, E, F and G. Each port pin is individually

user configurable, thus allowing multiple functions

per port. The ports are configured using PSDsoft

Express or by the MCU writing to on-chip registers

in the CSIOP space.

The topics discussed in this section are:

General Port architecture

Port operating modes

Port Configuration Registers (PCR)

Port Data Registers

Individual Port functionality.

General Port Architecture. The general archi-

tecture of the I/O Port block is shown in Figure 27.

Individual Port architectures are shown in Figure

29 to Figure 31. In general, once the purpose for a

port pin has been defined, that pin is no longer

available for other purposes. Exceptions are not-

ed.

As shown in Figure 27, the ports contain an output

multiplexer whose select signals are driven by the

configuration bits in the Control Registers (Ports E,

F and G only) and PSDsoft Express Configuration.

Inputs to the multiplexer include the following:

Output data from the Data Out register

Latched address outputs

CPLD Macrocell output

External Chip Select from the CPLD.

The Port Data Buffer (PDB) is a tri-state buffer that

allows only one source at a time to be read. The

Port Data Buffer (PDB) is connected to the Internal

Data Bus for feedback and can be read by the

MCU. The Data Out and Macrocell outputs, Direc-

tion Register and Control Register, and port pin in-

put are all connected to the Port Data Buffer

(PDB).

Figure 27. General I/O Port Architecture

DATA OUT

REG.

ADDRESS

MACROCELL OUTPUTS

ENABLE PRODUCT TERM (.OE)

EXT CS

ALE

READ MUX

CPLD - INPUT

CONTROL REG.

DIR REG.

INPUT

MACROCELL

ENABLE OUT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT PIN

DATA OUT

ADDRESS

AI02885

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