NRF52811-QCAA-R datasheet(146/444 Pages) NORDIC

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Peripherals

Decoder

Sequence 0

Sequence 1

Wave Counter

DATA RAM

COMP0

COMP1

COMP2

COMP3

SEQSTARTED[0]

SEQSTARTED[1]

SEQEND[0]

SEQEND[1]

SEQ[n].REFRESH

NEXTSTEP

PSEL.OUT[0]

PSEL.OUT[1]

PSEL.OUT[2]

PSEL.OUT[3]

PWM

Carry/Reload

PRESCALER

PWM_CLK

START

STOP

SEQSTART[0]

SEQSTART[1]

COUNTERTOP

STARTED

STOPPED

Figure 47: PWM module

6.12.1 Wave counter

The wave counter is responsible for generating the pulses at a duty cycle that depends on the compare

values, and at a frequency that depends on COUNTERTOP.

There is one common 15-bit counter with four compare channels. Thus, all four channels will share the

same period (PWM frequency), but can have individual duty cycle and polarity. The polarity is set by a

value read from RAM (see figure Decoder memory access modes on page 149). Whether the counter

counts up, or up and down, is controlled by the MODE register.

The timer top value is controlled by the COUNTERTOP register. This register value, in conjunction with the

selected PRESCALER of the PWM_CLK, will result in a given PWM period. A COUNTERTOP value smaller

than the compare setting will result in a state where no PWM edges are generated. OUT[n] is held high,

given that the polarity is set to FallingEdge. All compare registers are internal and can only be configured

through decoder presented later. COUNTERTOP can be safely written at any time.

Sampling follows the START task. If DECODER.LOAD=WaveForm, the register value is ignored and taken

from RAM instead (see section Decoder with EasyDMA on page 149 for more details). If DECODER.LOAD

is anything else than the WaveForm, it is sampled following a STARTSEQ[n] task and when loading a new

value from RAM during a sequence playback.

The following figure shows the counter operating in up mode (MODE=PWM_MODE_Up), with three PWM

channels with the same frequency but different duty cycle:

4454_140 v1.0

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