NRF52811-QCAA-R datasheet(148/444 Pages) NORDIC

148 / 444 page

Peripherals

Step width/Resolution:

Tsteps= TPWM_CLK

The following figure shows the counter operating in up-and-down mode

(MODE=PWM_MODE_UpAndDown), with two PWM channels with the same frequency but different duty

cycle and output polarity:

COUNTERTOP

COMP0

COMP1

OUT[0]

OUT[1]

Figure 49: PWM counter in up-and-down mode example

The counter starts decrementing to zero when COUNTERTOP is reached and will invert the OUT[n] when

compare value is hit for the second time. This results in a set of pulses that are center-aligned. The

following is the code for the counter in up-and-down mode example:

uint16_t pwm_seq[4] = {PWM_CH0_DUTY, PWM_CH1_DUTY, PWM_CH2_DUTY, PWM_CH3_DUTY};

NRF_PWM0->PSEL.OUT[0] = (first_pin << PWM_PSEL_OUT_PIN_Pos) |

(PWM_PSEL_OUT_CONNECT_Connected <<

PWM_PSEL_OUT_CONNECT_Pos);

NRF_PWM0->PSEL.OUT[1] = (second_pin << PWM_PSEL_OUT_PIN_Pos) |

(PWM_PSEL_OUT_CONNECT_Connected <<

PWM_PSEL_OUT_CONNECT_Pos);

NRF_PWM0->ENABLE

= (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);

NRF_PWM0->MODE

= (PWM_MODE_UPDOWN_UpAndDown << PWM_MODE_UPDOWN_Pos);

NRF_PWM0->PRESCALER

= (PWM_PRESCALER_PRESCALER_DIV_1 <<

PWM_PRESCALER_PRESCALER_Pos);

NRF_PWM0->COUNTERTOP = (16000 << PWM_COUNTERTOP_COUNTERTOP_Pos); //1 msec

NRF_PWM0->LOOP

= (PWM_LOOP_CNT_Disabled << PWM_LOOP_CNT_Pos);

NRF_PWM0->DECODER

= (PWM_DECODER_LOAD_Individual << PWM_DECODER_LOAD_Pos) |

(PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos);

NRF_PWM0->SEQ[0].PTR = ((uint32_t)(pwm_seq) << PWM_SEQ_PTR_PTR_Pos);

NRF_PWM0->SEQ[0].CNT = ((sizeof(pwm_seq) / sizeof(uint16_t)) <<

PWM_SEQ_CNT_CNT_Pos);

NRF_PWM0->SEQ[0].REFRESH = 0;

NRF_PWM0->SEQ[0].ENDDELAY = 0;

NRF_PWM0->TASKS_SEQSTART[0] = 1;

4454_140 v1.0

148

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